1. Field of the Invention:
This invention relates to an integrated circuit for level-shifting a small logical amplitude to a large logical amplitude.
2. Description of the Related Art:
FIG. 1 is an electric circuit diagram of a conventional example. This circuit shifts the level from a small logical amplitude V.sub.DD -V.sub.SS1 to a large logical amplitude V.sub.DD -V.sub.SS2. In FIG. 1, P1 represents a first P type MOS FET (hereinafter abbreviated as P1) and N1 represents a first N type MOS FET (hereinafter abbreviated as N1). The P1 and N1 are connected at their drains to each other and to a high voltage electric power source (in between V.sub.DD and V.sub.SS2).
Also, a second P type MOS FET (hereinafter abbreviated as P2) and a second N type MOS FET (hereinafter abbreviated as N2) are connected at their drains to each other and to the high voltage electric power source (in between V.sub.DD and V.sub.SS2).
INV1 is an inverter connected to a low voltage electric power source (in between V.sub. DD and V.sub.SS1) and to which an input of the small logical amplitude V.sub.DD -V.sub.SS1 is applied. The gates of the P1 and P2 are connected respectively to the output and input terminals of the inverter INV1.
Also, the gate of the N1 is connected to the common junction point of the P2 and N2, and the gate of the N2 is connected to the common junction point of the P1 and N1.
Next, the operation of this circuit is explained.
First assuming that the input of the inverter INV1 is high, that is, at V.sub.DD level, then the P1 turns on because its gate is low, that is, at V.sub.SS1 level, the P2 turns off because its gate is at V.sub.DD level, the drains of the P1 and N1 are at V.sub.DD level, and the drains of the P2 and N2 are at V.sub.SS2 level.
Then, when the input of the inverter INV1 becomes low, that is, at V.sub.SS1 level, the P1 turns off and the P2 turns on, causing the drains of the P2 and N2 to take an equilibrium level by their ON resistances. Therefore, the N1 turns on to discharge the charge on the gate of the N2. Thus, the N2 turns off.
In such a manner, the small logical amplitude V.sub.DD -V.sub.SS1 at the input of the inverter INV1 is converted into the large logical amplitude V.sub.DD -V.sub.SS2 at the drain of the P1 or P2.
In the above-described conventional example, the gates of the P1 and P2 are biased only at the small logical amplitude V.sub.DD -V.sub.SS1, while the gates of the N1 and N2 are biased at the large logical amplitude V.sub.DD -V.sub.SS2. To allow for flow of the same current, the Gm (current mu-factor) ratio between the P1 or P2 and the N1 or N2 must be given a large value. This leads to the necessity of increasing the size of the P1 and P2. As a result, the integrated circuit has a problem that its dimensions become objectionably bulky.
Meanwhile, in order to take this ratio at a smaller value, another circuit may be considered as shown in FIG. 2, wherein as the resistance components for the sources of the N1 and N2, use is made of third and fourth N type MOS FET N3 and N4 respectively to the gates of which a reference voltage Vref is applied. However, even this circuit has the gates of the N1 and N2 biased by a large logical level. Therefore, a considerably large ratio is required between the P1 or P2 and the N1 or N2.